BOSTON UNIVERSITY COLLEGE OF ENGINEERING Thesis A BALANCED-POWER DOMINO-STYLE STANDARD CELL LIBRARY FOR FINE-GRAIN ASYNCHRONOUS PIPELINED DESIGN TO RESIST DIFFERENTIAL POWER ANALYSIS ATTACKS by DANIEL

Despite the computational complexity of cryptographic algorithms, physical implementations of secure hardware leak information an attacker can use to determine sensitive data. Data-dependent power consumption is one example of leaked information that can reveal an algorithm’s secret key through a Differential Power Analysis (DPA) attack. Dual-rail asynchronous circuits have been proposed as a countermeasure to DPA because of their balanced data encoding and irregular transient power consumption compared to synchronous circuits. However, literature has shown these circuits are not necessarily immune to DPA unless special measures are taken to provide data-independent power consumption. The Sense Amplifier Based Logic (SABL) style has been proposed in literature for synchronous logic gates, but its effectiveness is diminished by asymmetrical discharge paths and transistor topology. This leaves less error margin for imbalances introduced by layout parasitics, placeand-route parasitics, and process variation. Therefore, this work proposes a new vi method to balance power consumption at the transistor level while integrating the benefits of fine-grain asynchronous pipelines. The new Balanced Symmetric with Discharge Tree (BSDT) style is two orders of magnitude more power balanced while maintaining 95% data throughput and 110% power consumption compared to conventional asynchronous logic gates. Proof-of-concept standard cell layouts are designed in 0.18μm CMOS technology that remain one order of magnitude more power-balanced after extracting parasitic capacitance, and are approximately six times more power-balanced than cells using previous balancing methods without extracted parasitic capacitance. The BSDT-style asynchronous logic cells are characterized by a library file for use with the Weaver automatic fine-grain asynchronous pipelined EDA tool to synthesize asynchronous circuits from standard synchronous HDL specification.